1. Field of the Invention
The present invention relates to electronic systems having multiple devices which communicate with each other. More particularly, the present invention relates to an apparatus that acts as an interface between multiple devices and a state machine handling data transfers into and out of memory.
2. The Prior Art
Modern electronic systems employing memory devices for data storage typically employ several types of devices such as central processing units, and video and sound devices, all of which need to have read/write access to memory.
FIG. 1 is a block diagram depicting a prior art electronic system employing several devices requiring read/write access to memory.
Referring to FIG. 1, MPEG signal source 10 provides an input signal to MPEG device 12 which processes that input signal, and provides output data to be stored in memory 14. Central processing unit 16, transport device 18, and other device 20 may also require access to memory 14 for the storage and retrieval of data. Transport device 18 may be defined as a device for receiving audio or video signals over antenna 22.
Each one of devices 12, 16, 18, and 20, will, at times, individually request memory access through memory controller 24 using interconnect paths 26, 28, 30, and 32 respectively. Because each device has different requirements for accessing and transmitting data, memory controller 24 has individual protocol translators 34, 36, 38, and 40 which are device specific, and which act on communications received from a given device, translating the information received into a format understandable by a state machine within memory controller 24 which handles the actual data transfers into and out of memory.
Although not applicable in every prior art case, the system previously described may be designed to reside on a single integrated circuit, the boundaries of which might be such as is defined by border 42.
The prior art apparatus, while being suitable for its intended purpose, has a significant drawback which is solved by the present invention. Because each of the devices MPEG device 12, CPU 16, transport device 18 and other device 20 have different requirements with respect to interfacing with memory, whenever one of these devices is replaced with a different device, or when a new device is added to the system, the memory controller 24 must be redesigned to accommodate the specific interface and data transfer requirements of the new device.
Prior art systems have translators 34, 36, 38, and 40 which are device specific, and which act on communications received from a given device, translating the information received into a format understandable by a state machine associated with memory controller 24. The redesign of the memory controller 24 to include the specific interface requirements of a new device is costly and time consuming.
In the prior art, when an existing device is replaced with a new device, or when a new device is added to the system, devices 12, 16, 18, and 20, as well as memory controller 24 would have to be redesigned. However, a system employing the present invention significantly reduces the amount of time which is required to redesign circuits when existing devices are replaced or new devices are added to a system such as described herein.
According to a first principle of the present invention, a common interface is provided between devices needing access to memory, and a state machine which manages the retrieval of data from memory. According to a second principle of the present invention, a universal interface is provided for devices requiring access to memory, the interface minimizing redesign efforts required when a new device is added or an old device is replaced. According to a third principle of the present invention, a universal memory interface is provided which decouples the requirements of the memory controller from other circuitry, thus allowing for significant design flexibility among devices requiring access to memory for storage and/or retrieval of data.
An electronic system is described herein, the system including at least two devices requiring access to memory, a memory controller, and a memory coupled to an output of the memory controller. The memory controller includes at least one input and at least one output. The at least one input is operatively coupled to at least two devices through a shared bus, and the at least one output is coupled to a memory. The shared bus includes a plurality of device select lines, a plurality of address lines, a plurality of write data lines, a plurality of read data lines, a plurality of read select lines, and at least two device_request lines.